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Table 11: Signal Description
Signal Name
Dir.
Pin
Description
These address lines along with the – REG signal are used to select the following:
The I/O port address registers within the CompactFlash TM Storage Card, the
memory mapped port address registers within the CompactFlash TM Storage Card,
A10 to A0
(PC Card Memory Mode)
I
8,10,11,12,
14,15,16,17,
18,19,20
a byte in the card ’ s information structure and its configuration control and
status registers.
In PC-Card mode, 16 bit ATA register file accesses (i.e. both -CE1 and -CE2 low)
do not work if A0 is high. A simple test will show the C-400 compatibility to a
certain host. If the C-400 cards can be recognized (Identify Device and MBR
data is read out successfully), then this PC card issue will likely not affect the
operation in this host. (1)
A10 to A0
(PC Card I/O Mode)
A2 to A0
(True IDE Mode)
BVD1
(PC Card Memory Mode)
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, only A[2:0] are used to select the one of eight registers in the
Task File, the remaining address lines should be grounded by the host.
This signal is asserted high, as BVD1 is not supported.
– STSCHG
(PC Card I/O Mode)
– PDIAG
(True IDE Mode)
BVD2
(PC Card Memory Mode)
– SPKR
(PC Card I/O Mode)
– DASP
(True IDE Mode)
D15-D0 (PC Card Memory
Mode)
D15-D0 (PC Card I/O Mode)
D15-D0 (True IDE Mode)
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
– INPACK
(PC Card Memory Mode)
I/O
I/O
I/O
46
45
31, 30, 29,
28, 27, 49,
48, 47, 6,
5, 4, 3, 2,
23, 22, 21
1, 50
This signal is asserted low to alert the host to changes in the READY and Write
Protect states, while the I/O interface is configured. Its use is controlled by the
Card Config and Status Register.
In the True IDE Mode, this input / output is the Pass Diagnostic signal in the
Master / Slave handshake protocol.
This signal is asserted high, as BVD2 is not supported.
This line is the Binary Audio output from the card. If the Card does not support
the Binary Audio function, this line should be held negated.
In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in
the Master/Slave handshake protocol.
These lines carry the Data, Commands and Status information between the host
and the controller. D0 is the LSB of the Even Byte of the Word. D8 is the LSB of
the Odd Byte of the Word.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, all Task File operations occur in byte mode on the low order
bus D[7:0] while all data transfers are 16 bit using D[15:0].
Ground.
Same for all modes.
Same for all modes.
This signal is not used in this mode.
The Input Acknowledge signal is asserted by the CompactFlash TM Storage Card
– INPACK
(PC Card I/O Mode)
when the card is selected and responding to an I/O read cycle at the address
that is on the address bus. This signal is used by the host to control the enable
of any input data buffers between the CompactFlash TM Storage Card and the
CPU.
This signal is a DMA Request that is used for DMA data transfers between host
and device. It shall be asserted by the device when it is ready to transfer data
to or from the host. For Multiword DMA transfers, the direction of data transfer
DMARQ
(True IDE Mode)
O
43
is controlled by – IORD and – IOWR. This signal is used in a handshake manner
with – DMACK, i.e., the device shall wait until the host asserts – DMACK before
negating DMARQ, and reasserting DMARQ if there is more data to transfer.
DMARQ shall not be driven when the device is not selected.
While a DMA operation is in progress, -CS0 and – CS1 shall be held negated and
the width of the transfers shall be 16 bits.
If there is no hardware support for DMA mode in the host, this output signal is
not used and should not be connected at the host. In this case, the BIOS must
report that DMA mode is not supported by the host so that device drivers will
not attempt DMA mode.
A host that does not support DMA mode and implements both PC card and
True-IDE modes of operation need not alter the PC card mode connections
while in True-IDE mode as long as this does not prevent proper operation in
any mode.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 13 of 102
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